Semiconductor device with dual gates and method of manufacturing the same

ABSTRACT

In a semiconductor device with dual gates and a method of manufacturing the same, a dielectric layer and first and second metallic conductive layers are successively formed on the semiconductor substrate having first and second regions. The second metallic conductive layer which is formed on the first metallic conductive layer of the second region is etched to form a metal pattern. The first metallic conductive layer is etched using the metal pattern as an etching mask. A polysilicon layer is formed on the dielectric layer and the metal pattern. The first gate electrode is formed by etching portions of the polysilicon layer, the metal pattern, and the first metallic conductive layer of the first region. The second gate electrode is formed by etching a portion of the polysilicon layer formed directly on the dielectric layer of the second region.

RELATED APPLICATIONS

This application is a divisional application of U.S. patent applicationSer. No. 11/497,998, filed on Aug. 1, 2006, which claims the benefit ofKorean patent application number 10-2005-70501, filed on Aug. 2, 2005,in the Korean Intellectual Property Office, the contents of whichapplications are incorporated herein in their entirety by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a method ofmanufacturing the same. More particularly, the present invention relatesto a complementary metal oxide semiconductor (CMOS) device with dualgates and a method of manufacturing the same.

2. Description of the Related Art

Metal Oxide Semiconductor (MOS) transistors can generally be classifiedinto N-channel Metal Oxide Semiconductor (NMOS) transistors andP-channel Metal Oxide Semiconductor (PMOS) transistors depending on achannel type. A CMOS transistor includes all characteristics of NMOS andPMOS since a CMOS transistor consists of an NMOS transistor and a PMOStransistor in a singular semiconductor device. Polysilicon has beentraditionally used as a gate electrode material for MOS-basedtransistors. The polysilicon gate electrode is typically doped witheither P⁺ or N⁺ to match the doped source/drain regions in CMOStechnology. However, as the size of semiconductor device continues todecrease, polysilicon becomes less effective as a material to be used asa gate electrode.

The polysilicon gate is highly doped so as to be nearly as conductive asmetal, while the solubility (or concentration) of dopants in thepolysilicon gate is limited to around 5×10²⁰ atoms/cm¹. Since thesolubility of dopants restricts the number of charge carriers in thepolysilicon gate, a depletion layer is formed at the interface betweenthe polysilicon gate and a gate dielectric layer when the gate isbiased. The depletion region in the polysilicon gate acts as anadditional capacitance in series with the gate dielectric capacitance.In other words, the depletion region increases the equivalent oxidethickness (EOT) of the transistor by at least 4 to 6 Å, therebydecreasing the driving current of the transistor.

Meanwhile, the efficacy of a silicon oxide film or a silicon oxynitridefilm conventionally used as the gate dielectric layer has reached itslimit because of the rapid decrease in size of semiconductor devices,and difficulties in securing the reliability of the gate dielectriclayer. For example, if the silicon oxide film becomes thinner than 20 Å,the gate leakage current is increased by quantum-mechanical directtunneling through the silicon oxide film, and the power consumptionincreases. Accordingly, there are limitations to the amount of reductionin the thickness of the gate dielectric layer formed of silicon oxide orsilicon oxynitride.

To overcome this problem, research with regard to the use of alternativegate dielectrics with dielectric constants (k) higher than silicon oxideor silicon oxynitride is being actively conducted. Dielectrics havingdielectric constants (k) higher than silicon oxide or silicon oxynitrideare referred to as high-k dielectrics. When the high-k dielectrics areused as the gate dielectric layer, the physical thickness of the gatedielectric layer can be large while the EOT can be scaled down forcompatibility with the other reduced feature sizes, and the leakagecurrent generated between the gate electrode and a channel region can bedecreased.

However, in MOS transistors utilizing high-k gate dielectrics andpolysilicon gate electrodes, defect states and numerous bulk traps,which are generated at the interface between a semiconductor substrateand a gate dielectric layer, capture electrons contributing conductionso that a Fermi level is pinned on a charge neutrality level or acentral portion of an energy band located around the charge neutralitylevel, thereby largely increasing the threshold voltage (Vth) of thetransistor.

The polysilicon gate depletion effect and the Fermi level pinningphenomenon occur more seriously in the case of PMOS transistors.Particularly, in the PMOS transistors, boron penetrates from thepolysilicon gate electrode doped with p+ through the gate dielectriclayer to the channel region of the semiconductor substrate, therebyvarying the flatband voltage (Vfb) and threshold voltage (Vth), anddeteriorating the device reliability.

The above-described problems may be solved forming a gate electrodehaving a similar work function as the one of either P or N dopedpolysilicon. The N doped polysilicon has a work function ofapproximately 4.2 eV whereas the P doped polysilicon has a work functionof approximately 5.1 eV. The difficulty is to choose a material which issuitable to both these work function values.

Another option is to form a gate electrode using two different materialswith one that is similar to the work function of the N-dopedpolysilicon, and the other that is similar to the work function of theP-doped polysilicon.

FIG. 1 is a cross-sectional view illustrating a semiconductor devicewith dual gate electrodes according to a conventional method.

Referring to FIG. 1, a gate dielectric layer 12 including a high-kdielectric such as HfO₂ is formed on a semiconductor substrate 10 havingPMOS and NMOS transistor regions.

A metal containing material such as tantalum nitride (TaN), which has awork function suitable to a PMOS transistor, is deposited on the gatedielectric layer 12 to form a metal gate layer. Then, the metal gatelayer is wet-etched to leave a portion of the metal gate layer only onthe PMOS transistor region.

After depositing a doped polysilicon layer on the gate dielectric layer12 and the remaining portion of the metal gate layer, the polysiliconlayer and the remaining portion of the metal gate layer are patterned bya lithography process. As a result, a gate stack 25 including a metalgate 14 and a polysilicon gate 16 a is formed on the PMOS transistorregion, while a polysilicon gate 16 b is formed on the NMOS transistorregion.

Here, a reference numeral 18 indicates source/drain regions of PMOStransistor and a reference numeral 20 indicates source/drain regions ofNMOS transistor.

In the conventional method described above, it is difficult to etch themetal gate layer. The unnecessary portion of the metal gate layer isremoved by a wet etching process in order to prevent the underlying gatedielectric layer from being damaged. In case that the metal gate layeris etched using a photoresist layer as an etching mask, the photoresistlayer cannot effectively serve as the etching mask because thephotoresist layer is removed by a wet etchant.

In the case where the metal gate layer is etched using a hard mask layerof silicon oxide, the underlying gate dielectric layer is removedtogether during a wet etching process of removing the hard mask layer.

In the case where the metal gate layer is etched using a hard mask layerof polysilicon, it is unnecessary to remove the polysilicon hard masklayer, thereby simplifying the process. However, since the polysiliconhard mask layer needs to be formed thicker than 300 Å due to thelimitation of the process uniformity, a difference in height between theNMOS transistor region and the PMOS transistor region becomes larger,and thus the etching process for gate patterning becomes difficult.

SUMMARY OF THE INVENTION

Example embodiments of the present invention provide a semiconductordevice with dual gates for simplifying processes and decreasing theheight difference between an NMOS transistor region and a PMOStransistor region.

Example embodiments of the present invention also provide a method ofmanufacturing a semiconductor device with dual gates for simplifyingprocesses and decreasing the height difference between an NMOStransistor region and a PMOS transistor region.

In one aspect, the present invention is directed to a semiconductordevice with dual gates, comprising: a semiconductor substrate having afirst region on which a MOS transistor of a first conductivity type willbe formed and a second region on which a MOS transistor of a secondconductivity type will be formed, a first gate dielectric layer on thesemiconductor substrate of the first region, a first gate electrode onthe first gate dielectric layer, the first gate electrode including alower metallic conductive pattern, an upper metallic conductive pattern,and a first polysilicon layer pattern, which are successively deposited,a second gate dielectric layer on the semiconductor substrate of thesecond region, a second gate electrode on the second gate dielectriclayer, the second gate electrode including a second polysilicon layerpattern. The lower metallic conductive pattern determines a workfunction of the first gate electrode.

In one embodiment, the lower metallic conductive pattern comprises ametal containing conductive material having a work function suitable tothe MOS transistor of the first conductivity type.

In another embodiment, the lower metallic conductive pattern comprisesany material selected from the group consisting of WN, TaN, TiN, Ni, Pd,Pt, Be, Ir, Te, Re, Ru and Rh.

In another embodiment, the upper metallic conductive pattern comprises ametal containing conductive material having an etch selectivity withrespect to the lower metallic conductive pattern.

In another embodiment, the upper metallic conductive pattern comprisesany material selected from the group consisting of TaN, WN, HfN, ZrN,TaSiN, TiSiN, NiSiN, Pd, Pt, Be, Ir, Te, Re, Ru, Rh, Al, Ag, Bi, Cd, Fe,Ta, Ga, Hf, In, Mn, Nb, Y and Zr.

In another embodiment, the upper metallic conductive pattern has athickness of less than about 100 Å.

In another embodiment, the first and second gate dielectric layerscomprise a high-k dielectric.

In another embodiment, the first conductivity type is P-type and thesecond conductivity type is N-type.

In another aspect, the present invention is directed to a semiconductordevice with dual gates, comprising: a semiconductor substrate having afirst region on which a MOS transistor of a first conductivity type willbe formed and a second region on which a MOS transistor of a secondconductivity type will be formed, a gate dielectric layer on thesemiconductor substrate in the first and second regions, a first gateelectrode on the gate dielectric layer of the first region, the firstgate electrode including a lower metallic conductive pattern, an uppermetallic conductive pattern, and a first polysilicon layer pattern,which are successively deposited, a second gate electrode on the gatedielectric layer of the second region, the second gate electrodeincluding a second polysilicon layer pattern. The lower metallicconductive pattern comprises WN, and the upper metallic conductivepattern comprises TaN.

In another aspect, the present invention is directed to a method ofmanufacturing a semiconductor device with dual gates, comprising:providing a semiconductor substrate having a first region on which a MOStransistor of a first conductivity type will be formed and a secondregion on which a MOS transistor of a second conductivity type will beformed, forming a dielectric layer, a first metallic conductive layerand a second metallic conductive layer on the first and second regions,etching the second metallic conductive layer formed on the firstmetallic conductive layer of the second region, thereby a metal patternis formed on the first metallic conductive layer of the first region,etching the first metallic conductive layer formed on the dielectriclayer of second region using the metal pattern as an etching mask,forming a polysilicon layer on the dielectric layer of the second regionand the metal pattern of the first region, forming a first gateelectrode by etching portions of the polysilicon layer, the metalpattern, and the first metallic conductive layer of the first region,the first gate electrode including a lower metallic conductive pattern,an upper metallic conductive pattern, and a polysilicon pattern, andforming a second gate electrode by etching a portion of the polysiliconlayer formed directly on the dielectric layer of the second region.

In one embodiment, the first metallic conductive layer comprises a metalcontaining conductive material having a work function suitable to theMOS transistor of the first conductivity type.

In another embodiment, the first metallic conductive layer comprises anymaterial selected from the group consisting of WN, TaN, TiN, Ni, Pd, Pt,Be, Ir, Te, Re, Ru and Rh.

In another embodiment, the second metallic conductive layer comprises ametal containing conductive material having an etch selectivity withrespect to the first metallic conductive layer.

In another embodiment, the second metallic conductive layer comprisesany material selected from the group consisting of TaN, WN, HfN, ZrN,TaSiN, TiSiN, NiSiN, Pd, Pt, Be, Ir, Te, Re, Ru, Rh, Al, Ag, Bi, Cd, Fe,Ta, Ga, Hf, In, Mn, Nb, Y and Zr.

In another embodiment, the second metallic conductive layer has athickness of less than about 100 Å.

In another embodiment, etching the second metallic conductive layerformed on the first metallic conductive layer of the second regioncomprises: forming a photoresist layer pattern on the second metallicconductive layer of the first region, removing the second metallicconductive layer of the second region using the photoresist layerpattern as an etching mask, and removing the photoresist layer pattern.

In another embodiment, etching the second metallic conductive layerformed on the first metallic conductive layer of the second regioncomprises: forming a hard mask layer on the second metallic conductivelayer, patterning the hard mask layer using a photoresist pattern as anetching mask to form a hard mask layer pattern on the second metallicconductive layer of the first region, removing the photoresist pattern,etching the second metallic conductive layer of the second region usingthe hard mask layer pattern as an etching mask, and removing the hardmask layer pattern.

In another embodiment, etching the first metallic conductive layerformed on the dielectric layer of second region using the metal patternas an etching mask is performed by a wet etching process.

In another embodiment, the dielectric layer comprises a high-kdielectric.

In another embodiment, the method, prior to forming the polysiliconlayer, further comprising performing a heat treatment process for curinga damage of the dielectric layer caused by etching the first metallicconductive layer of the second region.

In another embodiment, the heat treatment process is performed under anatmosphere including any one selected from the group consisting of N₂,NO, N₂O, O₂, NH₃ and H₂ or a combination thereof.

In another embodiment, the first conductivity type is P-type and thesecond conductivity type is N-type.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present inventionwill become readily apparent by reference to the following detaileddescription when considering in conjunction with the accompanyingdrawings, in which:

FIG. 1 is a cross-sectional view illustrating a semiconductor devicewith dual gates according to a conventional method;

FIG. 2 is a cross-sectional view illustrating a semiconductor devicewith dual gates according to a first example embodiment of the presentinvention;

FIGS. 3A and 3B are graphs illustrating electrical characteristics of agate electrode having a tungsten nitride layer;

FIGS. 4A to 4D are cross-sectional views illustrating a method ofmanufacturing a semiconductor device with dual gates according to asecond example embodiment of the present invention; and

FIGS. 5A to 5D are cross-sectional views illustrating a method ofmanufacturing a semiconductor device with dual gates according to athird example embodiment of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

The invention is described more fully hereinafter with reference to theaccompanying drawings, in which embodiments of the invention are shown.This invention may, however, be embodied in many different forms andshould not be construed as limited to the embodiments set forth herein.Rather, these embodiments are provided so that this disclosure will bethorough and complete. In the drawings, the sizes and relative sizes oflayers and regions may be exaggerated for clarity.

It will be understood that when an element or layer is referred to asbeing “on,” “connected to” or “coupled to” another element or layer, itcan be directly on, connected or coupled to the other element or layeror intervening elements or layers may be present. In contrast, when anelement is referred to as being “directly on,” “directly connected to”or “directly coupled to” another element or layer, there are nointervening elements or layers present. Like numbers refer to likeelements throughout. As used herein, the term “and/or” includes any andall combinations of one or more of the associated listed items.

It will be understood that, although the terms first, second, third etc.may be used herein to describe various elements, components, regions,layers and/or sections, these elements, components, regions, layersand/or sections should not be limited by these terms. These terms areonly used to distinguish one element, component, region, layer orsection from another region, layer or section. Thus, a first element,component, region, layer or section discussed below could be termed asecond element, component, region, layer or section without departingfrom the teachings of the present invention.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the exemplary term “below” can encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a,” “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

Embodiments of the invention are described herein with reference tocross-section illustrations that are schematic illustrations ofidealized embodiments (and intermediate structures) of the invention. Assuch, variations from the shapes of the illustrations as a result, forexample, of manufacturing techniques and/or tolerances, are to beexpected. Thus, embodiments of the invention should not be construed aslimited to the particular shapes of regions illustrated herein but areto include deviations in shapes that result, for example, frommanufacturing. For example, an implanted region illustrated as arectangle will, typically, have rounded or curved features and/or agradient of implant concentration at its edges rather than a binarychange from implanted to non-implanted region. Likewise, a buried regionformed by implantation may result in some implantation in the regionbetween the buried region and the surface through which the implantationtakes place. Thus, the regions illustrated in the figures are schematicin nature and their shapes are not intended to illustrate the actualshape of a region of a device and are not intended to limit the scope ofthe invention.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

Embodiment 1

FIG. 2 is a cross-sectional view illustrating a semiconductor devicewith dual gates according to a first example embodiment of the presentinvention.

Referring to FIG. 2, a semiconductor device according to an exampleembodiment of the present invention includes a semiconductor substrate100 having a first region 130 and a second region 132. A MOS transistorof a first conductivity type is formed on the first region 130 and a MOStransistor of a second conductivity type opposite to the firstconductivity type is formed on the second region 132.

The first conductivity type may be P-type and the second conductivitytype may be N-type.

A PMOS transistor including a first gate dielectric layer 102 a, a firstgate electrode 120 and first source/drain regions 112 is formed on thefirst region 130 of the semiconductor substrate 100, while an NMOStransistor including a second gate dielectric layer 102 b, a second gateelectrode 125 and second source/drain regions 114 is formed on thesecond region 132 of the semiconductor substrate 100.

The first gate electrode 120 of the PMOS transistor is formed of astacked structure including a lower metallic conductive pattern 104, anupper metallic conductive pattern 106 and a first polysilicon layerpattern 110 a, while the second gate electrode 125 of the NMOStransistor is formed of a single layer structure including a secondpolysilicon layer pattern 110 b, thereby realizing a CMOS device withdual gate electrodes having two different work functions where one wouldbe suitable to the PMOS transistor and the other suitable to the PMOStransistor.

Alternatively, a metal/polysilicon gate stack may be formed on the NMOStransistor region and a polysilicon gate electrode may be formed on thePMOS transistor region. However, it is preferred that themetal/polysilicon gate stack is formed on the PMOS transistor region andthe polysilicon gate electrode is formed on the NMOS transistor region,because the Fermi level pinning phenomenon and the polysilicon depletioneffect occur more seriously in the PMOS transistor as compared with theNMOS transistor and besides, the boron penetration also occurs in thePMOS transistor.

The conduction band for silicon lies at 4.1 eV below the vacuum level.The valence band lies at approximately 1.1 eV below the conduction bandfor silicon or at 5.2 eV below the vacuum level. The approximately 1.1eV difference between the valence and conduction bands for silicon isreferred to as the band-gap. The mid-gap is approximately half of theband-gap and is located approximately halfway between the conduction andvalence bands of the material.

A desirable work function for a gate electrode of an NMOS transistor isone which falls between the conduction band and mid-gap of thesemiconductor substrate and more preferably, is located betweenapproximately 4.0 eV and 4.4 eV. On the contrary, a desirable workfunction for a gate electrode of a PMOS transistor is one which fallsbetween the valence band and the mid-gap of the semiconductor substrateand more preferably, is between approximately 4.8 eV and 5.2 eV.

The lower metallic conductive pattern 104 is a layer that determines thework function of the first gate electrode 120 and may be formed from ametal-containing conductive material having the work function suitableto the PMOS transistor, e.g., the work function of more than about 4.6eV. In other words, the work function of the lower metallic conductivepattern 104, together with the doping level of the substrate 100,determines the threshold voltage of the PMOS transistor.

The lower metallic conductive pattern 104 may be formed from tungstennitride (WN). Alternatively, the lower metallic conductive pattern 104may be formed from tantalum nitride (TaN), titanium nitride (TiN),nickel (Ni), palladium (Pd), platinum (Pt), beryllium (Be), Iridium(Ir), tellurium (Te), rhenium (Re), Ruthenium (Ru), rhodium (Rh), or thelike.

The upper metallic conductive pattern 106 may serve as an etching maskfor the lower metallic conductive pattern 104 and may be formed from ametal-containing conductive material which does not adversely affect, orwhich can increase, the work function of the lower metallic conductivepattern 104.

The upper metallic conductive pattern 106 may be formed from tantalumnitride (TaN). Alternatively, the upper metallic conductive pattern 106may be formed from tungsten nitride (WN), hafnium nitride (HfN),Zirconium nitride (ZrN), tantalum silicon nitride (TaSiN), titaniumsilicon nitride (TiSiN), nickel silicon nitride (NiSiN), palladium (Pd),platinum (Pt), beryllium (Be), Iridium (Ir), tellurium (Te), rhenium(Re), Ruthenium (Ru), rhodium (Rh), aluminum (Al), argentum (Ag),bismuth (Bi), cadmium (Cd), ferrum (Fe), tantalum (Ta), gallium (Ga),hafnium (Hf), indium (In), manganese (Mn), niobium (Nb), yttrium (Y),zirconium (Zr), or the like.

In the conventional method, tantalum nitride (TaN) having a workfunction of approximately 4.8 eV and excellent thermal stability wasprimarily used as a metal-containing conductive material for themetal/polysilicon gate stack of the PMOS transistor. However, thetantalum nitride material is hardly removed during an etching processbecause of the low etch rate of tantalum nitride (TaN) with respect to awet solution.

Accordingly, in some embodiments of the present invention, the lowermetallic conductive pattern 104 determining the work function of thefirst gate electrode 120 for the PMOS transistor is formed from tungstennitride (WN) having a work function similar to that of the tantalumnitride (TaN) and exhibiting a high etch rate to the wet solution. Theupper metallic conductive pattern 106 serving as an etching mask of thelower metallic conductive pattern 104 is formed from tantalum nitride(TaN) having a high wet etch selectivity with respect to the tungstennitride (WN).

FIGS. 3A and 3B are graphs illustrating electrical characteristics of agate electrode having a tungsten nitride layer.

FIG. 3A is a graph illustrating a variation of capacitance (C) withrespect to a gate voltage (Vg). In this graph, the longitudinal axisrepresents a gate voltage [V] and the vertical axis represents acapacitance [pF]. The graph showing the relation between the capacitorand the voltage is referred to as C-V curve. In FIG. 3A, a symbol ▪indicates a C-V curve of a gate stack including a tantalum nitride layerhaving a thickness of about 100 Å and a polysilicon layer. A symbol indicates a C-V curve of a gate stack including a tungsten nitride layerhaving a thickness of about 100 Å and a polysilicon layer. A symbol ▴indicates a C-V curve of a gate stack including a tungsten nitride layerhaving a thickness of about 50 Å and a polysilicon layer. A symbol *indicates a C-V curve of a gate stack including a tungsten nitride layerhaving a thickness of about 50 Å, a tantalum nitride layer having athickness of about 50 Å and a polysilicon layer.

Referring to FIG. 3A, a flatband voltage (Vfb) of the tungstennitride/polysilicon gate stack is almost identical to that of thetantalum nitride/polysilicon gate stack, because the tungsten nitridelayer has a work function similar to that of the tantalum nitride layer(see the part shown in a dotted line).

Further, the tungsten nitride/polysilicon gate stack has the same C-Vcurve regardless of the thickness of the tungsten nitride layer.

Moreover, the C-V curve of the gate stack in which the tantalum nitridelayer serving as an etching mask remains on the tungsten nitride layerdetermining the work function of the gate electrode for the PMOStransistor is similar to the C-V curve of the gate stack having a singletungsten nitride layer.

FIG. 3B is a graph illustrating a leakage current density (Jg) withrespect to an equivalent oxide thickness (EOT). In this graph, thehorizontal axis represents an EOT [A] and the vertical axis represents aleakage current density [Å/μm²]. In FIG. 3B, a symbol □ indicates a casethat a polysilicon gate electrode is formed on a gate dielectric layerof silicon oxide (SiO₂). A symbol ◯ indicates a case that a polysilicongate electrode is formed on a gate dielectric layer of HfSiO. A symbol Δindicates a case that a gate stack including a tantalum nitride layerabout 100 Å thick and a polysilicon layer is formed on a gate dielectriclayer of HfSiO. A symbol * indicates a case that a gate stack includinga tungsten nitride layer about 50 Å thick, a tantalum nitride layerabout 50 Å thick and a polysilicon layer is formed on a gate dielectriclayer of HfSiO.

Referring to FIG. 3B, the gate stack of the example embodiment of thepresent invention, which includes the tungsten nitride layer, thetantalum nitride layer and the polysilicon layer, exhibits excellentfeatures in the aspect of EOT-Jg characteristics as compared with thesingle polysilicon gate electrode and has almost the identical propertyto that of the gate stack including the tantalum nitride layer and thepolysilicon layer.

As described above, the upper metallic conductive pattern 106 serving asan etching mask of the lower metallic conductive pattern 104 is formedof a material which does not adversely affect, or can increase, the workfunction of the lower metallic conductive pattern 104. As a result, thegate stack having a metallic gate of dual structure including the lowermetallic conductive pattern 104 and the upper metallic conductivepattern 106 exhibits electrical characteristics similar to those of thegate stack having a metallic gate of single layer including the lowermetallic conductive pattern or a metal containing material having thework function similar to that of the lower metallic conductive pattern.

Accordingly, the dual gate electrodes in accordance with the exampleembodiment of the present invention have the advantage of processsimplification, because the upper metallic conductive pattern 106serving as an etching mask of the lower metallic conductive pattern 104is used as a component of the gate stack without being removed.

Further, since the upper metallic conductive pattern 106 has a high etchselectivity with respect to the lower metallic conductive pattern 104,the upper metallic conductive pattern 106 can serve as a suitableetching mask even though it is formed relatively thinly, for example toa thickness of less than about 100 Å, thereby decreasing the heightdifference of the gate electrodes between the NMOS transistor region andthe PMOS transistor region.

Embodiment 2

FIGS. 4A to 4D are cross-sectional views illustrating a method ofmanufacturing a semiconductor device in accordance with a second exampleembodiment of the present invention.

Referring to FIG. 4A, a first region 130 and a second region 132 aredefined in a semiconductor substrate 100, a MOS transistor of a firstconductivity type is formed on the first region 130, and a MOStransistor of a second conductivity type opposite to the firstconductivity type is formed on the second region 132.

Here, the first conductivity type may be P-type and the secondconductivity type may be N-type.

Specifically, the first region 130 is an N-well on which a PMOStransistor will be formed, while the second region 132 is a P-well onwhich an NMOS transistor will be formed. One of skills in the art willrecognize that the location of the PMOS transistor region and the NMOStransistor region can be reversed.

Then, a high-k dielectric material is deposited to a thickness of lessthan about 50 Å on the semiconductor substrate 100, thereby forming adielectric layer 102 serving as a gate dielectric layer. The high-kdielectric material preferably has a dielectric constant greater than 5.More preferably, the high-k dielectric material has a dielectricconstant greater than about 10. Such “high-k” materials include oxidesof Group 4 and Group 5 metals (e.g., Ti, Zr, Hf, V, Nb, Ta), as well asmore complex oxides. The High-k dielectric materials can also includelanthanide oxides such as lanthanum oxide (k≈21), neodymium oxide (k≈16)and cerium oxide (k≈15). In other arrangements, it will be understoodthat the high-k dielectric material can include multiple materials,either as a ternary structure or a laminate of multiple high-kdielectric material layers.

Thus, the dielectric layer 102 may be formed of any materials known inthe art, such as hafnium oxide (HfO₂), zirconium oxide (ZrO₂), titaniumoxide (TiO₂), tantalum oxide (Ta₂O₅), niobium oxide (Nb₂O₃), aluminumoxide (Al₂O₃), cerium oxide (Ce₂O₃), lanthanum oxide (La₂O₃),praseodymium oxide (Pr₂O₃), dysprosium oxide (Dy₂O₃), erbium oxide(Er₂O₃), yttrium oxide (Y₂O₃), barium strontium titanate (BST),strontium titanate (ST), barium titanate (BT), lead zirconium titanate(PZT), strontium bismuth tantalate (SBT), and the like. The dielectriclayer 102 may be formed of multiple materials, for example as a ternarystructure or a laminate of multiple layers, including ZrSiO₄, ZrSiON,HfSiON, HfAlO, HfAlON, AlSlO, AlSiON, BaSiO₄, PbSiO₄, or the like.

The dielectric layer 102 may be formed by any suitable methods known inthe art, such as chemical vapor deposition (CVD), plasma-enhancedchemical vapor deposition (PECVD), high density plasma-chemical vapordeposition (HDP-CVD) and atomic layer deposition (ALD). In the presentlydescribed method embodiment, the dielectric layer 102 is formed by ALD.

Then, a metal containing conductive material having a work functionsuitable to the PMOS transistor is deposited to a thickness of less thanabout 100 Å on the dielectric layer 102, thereby forming a firstmetallic conductive layer 103. The first metallic conductive layer 103preferably may be formed from a conductive materials such as WN, TaN,TiN, Ni, Pd, Pt, Be, Ir, Te, Re, Ru, Rh, and the like, more preferablyfrom tungsten nitride (WN).

The first metallic conductive layer 103 may be deposited by any methodknown in the art. For the example, and without limitation, the firstmetallic conductive layer 103 may be deposited by chemical vapordeposition (CVD), physical vapor deposition (PVD), atomic layerdeposition (ALD), electrochemical deposition (ECD), metal organic CVD(MOCVD), plasma-enhanced CVD (PECVD) or plasma-enhanced ALD (PEALD). Inthis embodiment, the first metallic conductive layer 103 is formed to athickness of about 50 Å by the CVD.

Then, a metal containing conductive material having an etch selectivitywith respect to the material constituting the first metallic conductivelayer 103 is deposited to a thickness of less than about 100 Å on thefirst metallic conductive layer 103, thereby forming a second metallicconductive layer 105. Further, the material constituting the secondmetallic conductive layer 105 does not adversely affect, or canincrease, the work function of the first metallic conductive layer 103.

The second metallic conductive layer 105 may be formed from a conductivematerials such as TaN, WN, HfN, ZrN, TaSiN, TiSiN, NiSiN, Pb, Pt, Be,Ir, Te, Re, Ru, Rh, Al, Ag, Bi, Cd, Fe, Ta, Ga, Hf, In, Mn, Nb, Y, Zr,and the like, more preferably from tantalum nitride (TaN).

The second metallic conductive layer 105 may be deposited by any methodknown in the art. For the example, and without limitation, the secondmetallic conductive layer 105 may be deposited by CVD, PVD, ALD, ECD,MOCVD, PECVD or PEALD. In this method embodiment, the second metallicconductive layer 105 is formed to a thickness of about 50 Å by the PVD.

Referring to FIG. 4B, after coating a photoresist layer on the secondmetallic conductive layer 105, the photoresist layer is exposed anddeveloped to form a photoresist layer pattern 108 opening the secondregion 132 on which the NMOS transistor will be formed.

Then, using the photoresist layer pattern 108 as an etching mask, theexposed second metallic conductive layer 105 is etched by a dry etchingprocess with fluorine-based etching gas, thereby leaving a secondmetallic conductive layer portion 105 a on the first metallic conductivelayer 103 of the first region 130 on which the PMOS transistor will beformed.

Referring to FIG. 4C, the photoresist layer pattern 108 is removed byashing and stripping processes. Then, using the second metallicconductive layer portion 105 a as an etching mask, the exposed firstmetallic conductive layer 103 is etched to leave a first metallicconductive layer portion 103 a on the dielectric layer 102 of the firstregion 130 on which the PMOS transistor will be formed.

If the first metallic conductive layer 103 is dry-etched, the underlyingdielectric layer 102 is damaged severely. Thus, it is desirable that thefirst metallic conductive layer 103 is etched by a wet etching process.

With respect to a standard cleaning-1 (SC-1) where ammonium hydroxide(NH₄OH), hydrogen peroxide (H₂O₂) and water (H₂O) are mixed with a ratioof 1:4:20, which is typically used at the wet etching of metals, thetantalum nitride is scarcely removed because of a low etch rate of about1 Å/min, while the tungsten nitride has a high etch rate of about 1500Å/min. The tungsten nitride also exhibits a high etch rate of about 50Å/min with respect to a hydrogen peroxide solution where hydrogenperoxide (H₂O₂) and water (H₂O) are mixed with a ratio of about 1:5.

Accordingly, if the first metallic conductive layer 103 is formed oftungsten nitride having a high wet etch rate and the second metallicconductive layer 105 is formed of tantalum nitride having a high wetetch selectivity with respect to the tungsten nitride, the firstmetallic conductive layer 103 of the undesirable region, e.g., thesecond region 132 on which the NMOS transistor will be formed, can beeasily removed using the second metallic conductive layer portion 105 aas an etching mask.

Further, since the tantalum nitride of the second metallic conductivelayer 105 has a high etch selectivity with respect to the tungstennitride of the first metallic conductive layer 103 during a wet etchingprocess with the SC-1 solution or the hydrogen peroxide solution, thesecond metallic conductive layer 105 including the tantalum nitride canserve as a suitable etching mask even though formed to a relatively thinthickness of less than about 100 Å.

According to this method embodiment, the wet etching process using thehydrogen peroxide solution is performed to slightly decrease the etchrate of the tungsten nitride, because the tungsten nitride has a veryhigh etch rate to the SC-1 solution.

Referring to FIG. 4D, after leaving the first metallic conductive layerportion 103 a only on the first region 130 by etching the first metallicconductive layer 103 as described above, a polysilicon layer 109 dopedwith N-type is deposited on the dielectric layer 102 of the secondregion 132 and on the second metallic conductive layer portion 105 a.

The polysilicon layer 109 may be deposited by any suitable method knownin the art, such as CVD or low pressure CVD (LPCVD). The polysiliconlayer 109 may be deposited to a thickness of about 800˜1000 Å.

Before depositing the polysilicon layer 109, a heat treatment processmay be performed for curing the damage of the dielectric layer 102caused by the wet etching process of the first metallic conductive layer103. The heat treatment process may be carried out under an atmosphereincluding any one selected from the group consisting of N₂, NO, N₂O, O₂,NH₃ and H₂ or a combination thereof.

After depositing the polysilicon layer 109 as described above, a gatepatterning is carried out with respect to the polysilicon layer 109, thesecond metallic conductive layer portion 105 a and the first metallicconductive layer portion 103 a by a lithography process.

As a result, a first gate electrode 120 of the PMOS transistor is on thefirst region 130 and a second gate electrode 125 of the NMOS transistoris on the second region 132 as shown in FIG. 2. The first gate electrode120 includes a lower metallic conductive pattern 104 of the firstmetallic conductive layer, an upper metallic conductive pattern 106 ofthe second metallic conductive layer and a first polysilicon layerpattern 110 a, which are successively stacked. The second gate electrode125 includes a second polysilicon layer pattern 110 b.

During the gate patterning process, the underlying dielectric layer isetched together to thereby form a first gate dielectric layer 102 a ofthe PMOS transistor and a second gate dielectric layer 102 b of the NMOStransistor.

According to the conventional method of manufacturing dual gates asshown in FIG. 1, the mask layer used for etching the metal gate layershould be removed, so that the underlying gate dielectric layer isremoved together.

On the contrary, according to this present method embodiment of thepresent invention, it is unnecessary to remove the second metallicconductive layer 105 serving as an etching mask of the first metallicconductive layer 103, because the second metallic conductive layer 105is formed of a conductive material, which does not adversely affect, orcan increase, the work function of the first metallic conductive layer103. Therefore, the process of removing the second metallic conductivelayer 105 can be omitted to prevent the damage of the dielectric layer102 and to simplify the fabrication process.

Further, since the second metallic conductive layer 105 has a high etchselectivity with respect to the first metallic conductive layer 103, thesecond metallic conductive layer 105 can serve as a suitable etchingmask even though formed relatively thinly to a thickness of less than100 Å. Accordingly, the height difference of the gate electrodes betweenthe NMOS transistor region and the PMOS transistor region can bedecreased so as to readily perform the etching process for gatepatterning.

Meanwhile, according to this present method embodiment of the presentinvention, the first and second gate electrodes 120 and 125 may beformed substantially simultaneously. However, the first and second gateelectrodes 120 and 125 may be respectively formed by repeatedlyperforming a lithography process.

Embodiment 3

FIGS. 5A to 5D are cross-sectional views illustrating a method ofmanufacturing a semiconductor device in accordance with a third exampleembodiment of the present invention.

Referring to FIG. 5A, in the same manner as in the second embodiment ofFIGS. 4A-4D, a dielectric layer 102, a first metallic conductive layer103 and a second metallic conductive layer 105 are successively formedon a semiconductor substrate 100 having a first region 130 on which aPMOS transistor will be formed and a second region 132 on which an NMOStransistor will be formed.

The dielectric layer 102 is characterized by a high dielectric constantmaterial. The dielectric layer 102 may be formed of any material knownin the art, including HfO₂, ZrO₂, TiO₂, Ta₂O₅, Nb₂O₃, Al₂O₃, Ce₂O₃,La₂O₃, Pr₂O₃, Dy₂O₃, Er₂O₃, Y₂O₃, BST, ST, BT, PZT, SBT, and the like.The dielectric layer 102 may be formed of multiple materials, forexample as a ternary structure or a laminate of multiple layers,including ZrSiO₄, ZrSiON, HfSiON, HfAlO, HfAlON, AlSiO, AlSiON, BaSiO₄,PbSiO₄, and the like. The dielectric layer 102 may be formed by anysuitable methods known in the art, such as CVD, PECVD, HDP-CVD and ALD.In this embodiment, a high-k dielectric material is deposited to athickness of less than about 50 Å by ALD, thereby forming the dielectriclayer 102.

The first metallic conductive layer 103 is a layer that determines awork function of a gate electrode for the PMOS transistor. The firstmetallic conductive layer 103 may be formed from a conductive materialsuch as WN. Alternatively, the first metallic conductive layer 103 maybe formed from TaN, TiN, Ni, Pd, Pt, Be, Ir, Te, Re, Ru, Rh or the like.The first metallic conductive layer 103 may be deposited by any of themethods known in the art, such as CVD, PVD, ALD, ECD, MOCVD, PECVD andPEALD. In this embodiment, the first metallic conductive layer 103 isformed by depositing tungsten nitride (WN) to a thickness of about 50 Åusing the CVD method.

The second metallic conductive layer 105 operates as an etching masklayer of the first metallic conductive layer 103. The second metallicconductive layer 105 may be formed of a conductive material, such asTaN, having an etch selectivity with respect to the first metallicconductive layer 103. Alternatively, the second metallic conductivelayer 105 may be formed of WN, HfN, ZrN, TaSiN, TiSiN, NiSiN, Pb, Pt,Be, Ir, Te, Re, Ru, Rh, Al, Ag, Bi, Cd, Fe, Ta, Ga, Hf, In, Mn, Nb, Y,Zr, or the like.

Further, the material constituting the second metallic conductive layer105 does not adversely affect the work function of the first metallicconductive layer 103 or can increase the work function. The secondmetallic conductive layer 105 may be deposited by any methods known inthe art, such as CVD, PVD, ALD, ECD, MOCVD, PECVD and PEALD. In thisembodiment, the second metallic conductive layer 105 is formed bydepositing tantalum nitride (TaN) to a thickness of less than 50 Å usingthe PVD method.

Then, silicon oxide is deposited to a thickness of about 200 Å on thesecond metallic conductive layer 105, thereby forming a hard mask layer115. The hard mask layer 115 is formed by an ALD method so that thesilicon oxide is deposited at a low temperature and exhibits a high wetetch rate.

Referring to FIG. 5B, after coating a photoresist layer on the hard masklayer 115, the photoresist layer is exposed and developed to form aphotoresist layer pattern 118 opening the second region 132 on which theNMOS transistor will be formed.

Then, using the photoresist layer pattern 118 as an etching mask, theexposed hard mask layer 115 is etched to form a hard mask layer pattern116 on the second metallic conductive layer 105 of the first region 130on which the PMOS transistor will be formed.

In case that the hard mask layer 115 is formed of the ALD oxide, thehard mask layer 115 may be etched by a wet etching process with 200:1diluted hydrofluoric acid (HF), because the ALD oxide has a high wetetch rate with respect to the diluted hydrofluoric acid (HF).

Referring to FIG. 5C, the photoresist layer pattern 118 is removed byashing and stripping processes. Then, the exposed second metallicconductive layer 105 is etched by a dry etching process using the hardmask layer pattern 116 as an etching mask, thereby leaving a secondmetallic conductive layer portion 105 a on the first metallic conductivelayer 103 of the first region 130 on which the PMOS transistor will beformed.

In the second embodiment described above, the second metallic conductivelayer 105 is etched using the photoresist layer pattern so that the etchby-products such as polymer may be formed on sidewalls of the secondmetallic conductive layer portion 105 a. Accordingly, this problem ofpolymer formation can be prevented by etching the second metallicconductive layer 105 using the hard mask layer pattern 116 including thesilicon oxide.

Referring to FIG. 5D, the hard mask layer pattern 116 is removed by anoverall etch-back process. Then, the exposed first metallic conductivelayer 103 is etched by a wet etching process using the second metallicconductive layer portion 105 a as an etching mask, thereby leaving afirst metallic conductive layer portion 103 a on the dielectric layer102 of the first region 130 on which the PMOS transistor will be formed.

The tantalum nitride exhibits a high etch selectivity with respect tothe tungsten nitride during a wet etching process with SC-1 solution orhydrogen peroxide solution. In this embodiment, the first metallicconductive layer 103 is etched by a wet etching process using thehydrogen peroxide solution, because the tungsten nitride has a very highetch rate to the SC-1 solution.

After leaving the first metallic conductive layer portion 103 a only onthe first region 130 as described above, a polysilicon layer doped withN-type is deposited on the dielectric layer 102 of the second region 132and on the second metallic conductive layer portion 105 a.

The polysilicon layer may be deposited by any suitable methods known inthe art, such as CVD and LPCVD. The polysilicon layer is deposited to athickness of about 800˜1000 Å.

A heat treatment process may be performed for curing the damage of thedielectric layer 102 caused by the wet etching process of the firstmetallic conductive layer 103, if necessary, before depositing thepolysilicon layer. The heat treatment process may be carried out underan atmosphere including any one selected from the group consisting ofN₂, NO, N₂O, O₂, NH₃ and H₂ or a combination thereof.

Then, a gate patterning is carried out with respect to the polysiliconlayer, the second metallic conductive layer portion 105 a and the firstmetallic conductive layer portion 103 a by a lithography process,thereby forming a first gate electrode 120 of the PMOS transistor on thefirst region 130 and a second gate electrode 125 of the NMOS transistoron the second region 132, as shown in FIG. 2. The first gate electrode120 includes a lower metallic conductive pattern 104, an upper metallicconductive pattern 106 and a first polysilicon layer pattern 110 a,which are successively stacked. The second gate electrode 125 includes asecond polysilicon layer pattern 110 b.

During the gate patterning process, the underlying dielectric layer isetched together to thereby form a first gate dielectric layer 102 a ofthe PMOS transistor and a second gate dielectric layer 102 b of the NMOStransistor.

According to the example embodiments of the present invention asdescribed above, the first gate electrode of stacked structure includingthe lower metallic conductive pattern, the upper metallic conductivepattern and the first polysilicon layer pattern is formed on the PMOStransistor region, while the second gate electrode of single layerstructure including the second polysilicon layer pattern is formed onthe NMOS transistor region. As a result, a semiconductor device withdual gate electrodes, that is two different types of gate electrodestructures, can be realized.

The lower metallic conductive pattern determines the work function ofthe first gate electrode and the upper metallic conductive patternserves as an etching mask of the lower metallic conductive pattern.

Since the upper metallic conductive pattern is formed from a conductivematerial which does not adversely affect the work function of the lowermetallic conductive pattern, or can increase the work function, aprocess of removing the upper metallic conductive pattern can be omittedto prevent the gate dielectric layer from being damaged, and to simplifythe processes.

Further, since the upper metallic conductive pattern having a high etchselectivity with respect to the lower metallic conductive pattern can beformed relatively thinly, the height difference of the gate electrodesbetween the NMOS transistor region and the PMOS transistor region can bedecreased to thereby readily perform the etching process for gatepatterning.

While this invention has been particularly shown and described withreferences to preferred embodiments thereof, it will be understood bythose skilled in the art that various changes in form and details may bemade herein without departing from the spirit and scope of the inventionas defined by the appended claims.

1. A semiconductor device with dual gates, comprising: a semiconductorsubstrate having a first region on which a MOS transistor of a firstconductivity type will be formed and a second region on which a MOStransistor of a second conductivity type will be formed; a first gatedielectric layer on the semiconductor substrate of the first region; afirst gate electrode on the first gate dielectric layer, the first gateelectrode including a lower metallic conductive pattern, an uppermetallic conductive pattern, and a first polysilicon layer pattern,which are successively deposited; a second gate dielectric layer on thesemiconductor substrate of the second region; a second gate electrode onthe second gate dielectric layer, the second gate electrode including asecond polysilicon layer pattern; and wherein the lower metallicconductive pattern determines a work function of the first gateelectrode.
 2. The semiconductor device of claim 1, wherein the lowermetallic conductive pattern comprises a metal containing conductivematerial having a work function suitable to the MOS transistor of thefirst conductivity type.
 3. The semiconductor device of claim 1, whereinthe lower metallic conductive pattern comprises any material selectedfrom the group consisting of WN, TaN, TiN, Ni, Pd, Pt, Be, Ir, Te, Re,Ru and Rh.
 4. The semiconductor device of claim 1, wherein the uppermetallic conductive pattern comprises a metal containing conductivematerial having an etch selectivity with respect to the lower metallicconductive pattern.
 5. The semiconductor device of claim 1, wherein theupper metallic conductive pattern comprises any material selected fromthe group consisting of TaN, WN, HfN, ZrN, TaSiN, TiSiN, NiSiN, Pd, Pt,Be, Ir, Te, Re, Ru, Rh, Al, Ag, Bi, Cd, Fe, Ta, Ga, Hf, In, Mn, Nb, Yand Zr.
 6. The semiconductor device of claim 1, wherein the uppermetallic conductive pattern has a thickness of less than about 100 Å. 7.The semiconductor device of claim 1, wherein the first and second gatedielectric layers comprise a high-k dielectric.
 8. The semiconductordevice of claim 1, wherein the first conductivity type is P-type and thesecond conductivity type is N-type.
 9. A semiconductor device with dualgates, comprising: a semiconductor substrate having a first region onwhich a MOS transistor of a first conductivity type will be formed and asecond region on which a MOS transistor of a second conductivity typewill be formed; a gate dielectric layer on the semiconductor substratein the first and second regions; a first gate electrode on the gatedielectric layer of the first region, the first gate electrode includinga lower metallic conductive pattern, an upper metallic conductivepattern, and a first polysilicon layer pattern, which are successivelydeposited; a second gate electrode on the gate dielectric layer of thesecond region, the second gate electrode including a second polysiliconlayer pattern; wherein the lower metallic conductive pattern comprisesWN; and wherein the upper metallic conductive pattern comprises TaN.